Many integrated circuit devices control internal operations according to one or more timing signals. For example, an integrated circuit may typically receive an external “clock” signal, and control various operations based on such a clock signal.
In some cases it can be desirable to operate different portions of an integrated circuit according to different timing signals. For example, certain circuit portions may operate based on a rising edge of a clock signal, while other portions may operate based on a falling edge of a clock signal. In some cases, data paths from different portions may have to be combined. Conventionally, combining data from paths controlled by different timing signals can lead to drawbacks in performance.
A novel approach to addressing different timing paths will now be described with reference to FIGS. 12 and 13.
FIG. 12 is a block diagram showing a timing arrangement for a content addressable memory (CAM) device. In FIG. 12, a CAM device is designated by the general reference character 1200, and may include a first circuit portion 1202 that operates according to a first timing signal FCLK and a second circuit portion 1204 that operates according to a second timing signal RCLK. In FIG. 12, first and second circuit portions (1202 and 1204) may comprise CAM arrays that receive key values (comparands) for comparison with entries that store data values.
In FIG. 12, a first timing signal FCLK may be generated by a first phase lock loop (PLL) circuit 1206, while a second timing signal RCLK may be generated by a second PLL circuit 1208. Both a first and second PLL circuit (1206 and 1208) may receive an external clock signal EXT CLK.
A first PLL circuit 1206 may be considered a “falling” edge circuit, and may generate a periodic signal FCLK having a transition corresponding to falling edges of a external clock signal EXT CLK. In FIG. 12, a first PLL circuit 1206 may generate a first timing signal FCLK having a “50/50” duty cycle. That is, a timing signal FCLK can transition high for essentially the same amount of time the signal transitions low. A first timing signal FCLK may control a first circuit portion 1202.
In a similar fashion, a second PLL circuit 1208 may be considered a “rising” edge circuit, and may generate a periodic signal RCLK having a transition corresponding to rising edges of an external clock signal EXT CLK. In FIG. 12, a second PLL circuit 1208 may generate a second timing signal RCLK having a “50/50” duty cycle. That is, a timing signal RCLK can transition high for essentially the same amount of time it transitions low. A second timing signal RCLK may control a second circuit portion 1204.
A CAM 1200 may also include a latch 1210 and registers 1212a and 1212b. A latch 1210 may receive data from a first circuit portion 1202, and latch such data according to first timing signal FCLK. A register 1212a may receive data from a latch 1210, and load and eventually output such data as result data RESA. A register 1212b may receive data from second circuit portion 1204, and load and eventually output such data as result data RESB. Both registers (1212a and 1212b) may latch and then output received data according to second timing signal RCLK.
The operation of the circuit of FIG. 12 will now be described with reference to FIG. 13. FIG. 13 is a timing diagram divided into two portions 1300 and 1302. Portion 1300 shows an operation when a received timing signal EXT CLK has a “50/50” duty cycle. Portion 1302 shows an operation when a received timing signal EXT CLK has a “40/60” duty cycle. That is, EXT CLK transitions high for 40% of a clock cycle, and low for a remaining 60% of a clock cycle.
Both portions 1300 and 1302 of FIG. 13 show an external clock signal EXT CLK, a second timing signal RCLK, a second circuit portion ARRAY B operation, a first timing signal FCLK, and a first circuit portion ARRAY A operation. It is noted that second timing signal RCLK has a 50/50 duty cycle with a rising edge corresponding to a rising edge of the external clock signal EXT CLK. Similarly, first timing signal FCLK has a 50/50 duty cycle with a falling edge corresponding to a falling edge of the external clock signal EXT CLK.
Portion 1300 shows an ideal operation, in which data passes from a latch 1210, that operates according to a first timing signal FCLK, to a register 1212a, that operates according to a second timing signal RCLK.
In an ideal operation 1300, at time t0, a first timing signal FCLK can transition high. As a result, a first circuit portion 1202 may evaluate a key (i.e., perform a compare operation) and generate result data. At the same essential time, because an external clock has a 50/50 duty cycle, a second timing signal RCLK may also transition high. As a result, a second circuit portion 1204 may enter a precharge state.
Referring still to ideal operation 1300, between times t0 and t1, data may be output from a first circuit portion 1202. Further, because first timing signal FCLK is high, latch 1210 may be in a transparent state and may latch output data from a first circuit portion 1202. Conversely, because second timing signal RCLK is high at this time, registers 1212a and 1212b may output stored data, but not load new data. Thus, data output from latch 1210 may not be loaded into register 1212a, and data output from second circuit portion 1202 may not be loaded in register 1212b. 
Referring still to ideal operation 1300, at time t1, a first timing signal FCLK can transition low. As a result, a first circuit portion 1202 may enter a precharge state. At the same essential time, because an external clock has a 50/50 duty cycle, a second timing signal RCLK may also transition low. As a result, a second circuit portion 1204 may evaluate a key (i.e., perform a compare operation) and generate result data.
Referring yet still to ideal operation 1300, after time t1, because first timing signal FCLK is low, latch 1210 may be in an opaque state, and thus can output latched data but not latch any new input data. Further, because second timing signal RCLK is low at this time, registers 1212a and 1212b may load new data. Thus, data output from latch 1210 can be loaded in register 1212a, and data output from second circuit portion 1204 can be loaded in register 1212b. 
A drawback to the timing arrangements is shown in portion 1302 of FIG. 13. In portion 1302, a “high” portion of external clock signal EXT CLK is shorter in duration than a low portion (i.e., 40/60 duty cycle). However, first and second timing signals (FCLK and RCLK) maintain 50/50 duty cycles. Consequently, a rising edge of a first timing signal FCLK can “lead” (transition high) before a rising edge of a second timing signal (RCLK).
Referring now to portion 1302 of FIG. 13, at time t2 a first timing signal FCLK can transition high prior to second timing signal RCLK. As a result, a latch 1210 may enter a transparent state. However, at the same time, a second timing signal RCLK may be low, and not transition high until time t3. Thus, registers 1212a and 1212b may load input data. This is in contrast to a case in which registers 1212a and 1212b may be “closed” at this time. Such an arrangement may result in data currently latched within a register 1212a possibly being corrupted by data output from transparent latch 1210.
It would therefore be desirable to arrive at a way of addressing the above drawbacks to devices that include multiple timing signals.